emc

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EMC Pre-Compliance Skill

EMC预合规分析工具

Automated EMC risk analysis for KiCad PCB designs. Identifies the most common causes of EMC test failures using geometric rule checks, analytical emission formulas, and optional SPICE simulation.

This is a risk analyzer, not a compliance predictor. It catches ~70% of common EMC design mistakes before fabrication. It cannot guarantee FCC/CISPR compliance — only a calibrated measurement in an accredited lab can do that. But it can reduce the first-spin failure rate from ~50% toward ~20-30%, potentially saving $5K-$50K per avoided board respin.

针对KiCad PCB设计的自动化EMC风险分析工具。通过几何规则检查、分析发射公式和可选的SPICE仿真，识别导致EMC测试失败的最常见原因。

这是一款风险分析工具，而非合规预测工具。 它能在制造前发现约70%的常见EMC设计错误。无法保证符合FCC/CISPR标准——只有经认可实验室的校准测量才能做到这一点。但它可以将首次试制失败率从约50%降低至20%-30%，每次避免电路板重新试制可能节省5000至50000美元。

Related Skills

Skill	Purpose
`kicad`	Schematic/PCB analysis — produces the analyzer JSON this skill consumes
`kicad` (thermal)	Thermal hotspot analysis — MLCC derating and ferrite/inductor overheating findings can amplify EMC decoupling and filter issues (an over-stressed MLCC degrades; a hot ferrite drifts impedance). Worth cross-checking when EMC flags DC-001/DC-002 or EF-001/EF-002.
`spice`	SPICE simulation — provides simulator backend for SPICE-enhanced PDN/filter checks

工具	用途
`kicad`	原理图/PCB分析——生成本工具所需的分析器JSON文件
`kicad` （热分析）	热热点分析——MLCC降额和铁氧体/电感器过热问题会加剧EMC去耦和滤波问题（过载的MLCC性能会下降；过热的铁氧体阻抗会漂移）。当EMC标记DC-001/DC-002或EF-001/EF-002时，值得交叉检查。
`spice`	SPICE仿真——为SPICE增强型PDN/滤波检查提供仿真后端

Requirements

要求

Python 3.10+ — stdlib only, no pip dependencies
Schematic analyzer JSON — from
```
analyze_schematic.py --output
```
PCB analyzer JSON — from
```
analyze_pcb.py --full --output
```
(recommended with
```
--full
```
)
SPICE simulator (optional) — ngspice, LTspice, or Xyce for SPICE-enhanced PDN/filter checks. Auto-detected. Without one, analytical models run unchanged.

Python 3.10+ — 仅使用标准库，无需pip依赖
原理图分析器JSON — 来自
```
analyze_schematic.py --output
```
PCB分析器JSON — 来自
```
analyze_pcb.py --full --output
```
（推荐使用
```
--full
```
参数）
SPICE仿真器（可选）——ngspice、LTspice或Xyce，用于SPICE增强型PDN/滤波检查。会自动检测。如果没有，分析模型将保持不变运行。

Workflow

工作流程

Step 1: Run the analyzers

步骤1：运行分析器

bash

python3 <kicad-skill-path>/scripts/analyze_schematic.py design.kicad_sch --analysis-dir analysis/
python3 <kicad-skill-path>/scripts/analyze_pcb.py design.kicad_pcb --full --analysis-dir analysis/

bash

python3 <kicad工具路径>/scripts/analyze_schematic.py design.kicad_sch --analysis-dir analysis/
python3 <kicad工具路径>/scripts/analyze_pcb.py design.kicad_pcb --full --analysis-dir analysis/

Step 2: Run EMC analysis

步骤2：运行EMC分析

Pass

--analysis-dir analysis/

— the script auto-resolves

schematic.json

and

pcb.json

from the manifest's current run, and writes

emc.json

into the same folder so the manifest tracks it.

bash

undefined

传入

--analysis-dir analysis/

——脚本会自动从当前运行的清单中解析

schematic.json

和

pcb.json

，并将

emc.json

写入同一文件夹，以便清单跟踪。

bash

undefined

Recommended: auto-resolve inputs from the current run

推荐：自动解析当前运行的输入文件

python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/

python3 <工具路径>/scripts/analyze_emc.py --analysis-dir analysis/

Equivalent — explicit paths still accepted (and required if you want to

等效方式——仍接受显式路径（如果指向非当前运行或覆盖某个输入文件，则为必填）

point at a non-current run or override one input)

—

python3 <skill-path>/scripts/analyze_emc.py
--schematic analysis/<run_id>/schematic.json
--pcb analysis/<run_id>/pcb.json
--analysis-dir analysis/

python3 <工具路径>/scripts/analyze_emc.py
--schematic analysis/<运行ID>/schematic.json
--pcb analysis/<运行ID>/pcb.json
--analysis-dir analysis/

One-off JSON (bypasses the cache)

一次性JSON（绕过缓存）

python3 <skill-path>/scripts/analyze_emc.py --schematic schematic.json --pcb pcb.json --output emc.json

python3 <工具路径>/scripts/analyze_emc.py --schematic schematic.json --pcb pcb.json --output emc.json

SPICE-enhanced (improved PDN and filter accuracy)

SPICE增强版（提升PDN和滤波精度）

python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --spice-enhanced

python3 <工具路径>/scripts/analyze_emc.py --analysis-dir analysis/ --spice-enhanced

Select target standard

选择目标标准

python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --standard cispr-class-b

python3 <工具路径>/scripts/analyze_emc.py --analysis-dir analysis/ --standard cispr-class-b

Select target market (sets all applicable standards)

选择目标市场（设置所有适用标准）

python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --market eu

python3 <工具路径>/scripts/analyze_emc.py --analysis-dir analysis/ --market eu

Filter by severity

按严重程度过滤

python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --severity high

python3 <工具路径>/scripts/analyze_emc.py --analysis-dir analysis/ --severity high

Human-readable text output

人类可读文本输出

python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --text

undefined

python3 <工具路径>/scripts/analyze_emc.py --analysis-dir analysis/ --text

undefined

Step 3: Interpret results

步骤3：解读结果

Read the JSON report and incorporate findings into the design review. Each finding has a severity, rule ID, description, and actionable recommendation. See "Interpreting Results" below.

阅读JSON报告并将结果纳入设计评审。每个发现都包含严重程度、规则ID、描述和可操作建议。详见下方“解读结果”部分。

What Gets Checked

检查内容

44 rule IDs across 18 categories. Each rule has a specific threshold, rationale, and source citation — see

references/pcb-emc-rules.md

for full details.

Category	Rules	What it detects
Ground plane	GP-001 to GP-005	Signal crossing voids, zone fragmentation, missing ground planes, low fill ratio, multiple ground domains
Decoupling	DC-001 to DC-003	Cap too far from IC, IC with no decoupling cap, cap too far from via
I/O filtering	IO-001, IO-002	Connector without filtering, insufficient ground pins
Switching EMC	SW-001 to SW-003	Harmonic overlap, switching node copper area, input cap loop area
Clock routing	CK-001 to CK-003	Clock on outer layer, long trace, clock near connector
Via stitching	VS-001	Ground via spacing exceeds λ/20 at highest frequency
Stackup	SU-001 to SU-003	Adjacent signal layers, signal far from reference plane, thin interplane capacitance
Diff pair	DP-001 to DP-004	Intra-pair skew vs protocol limits, CM radiation, reference plane change, outer layer routing
Board edge	BE-001 to BE-003	Signal near edge, incomplete ground pour ring, connector area stitching
PDN impedance	PD-001 to PD-004	Anti-resonance peaks, distributed rail impedance at IC load points, cross-rail coupling from downstream switching regulators
Return path	RP-001	Layer transition via without nearby ground stitching via
Crosstalk	XT-001	3H spacing violation, aggressor-victim pairs
EMI filter	EF-001, EF-002	Filter cutoff too close to switching frequency (analytical or SPICE insertion loss)
ESD path	ES-001, ES-002	TVS too far from connector, insufficient ground vias near TVS
Thermal-EMC	TH-001, TH-002	MLCC DC bias derating (SRF shift), ferrite near heat source
Shielding	SH-001	Connector aperture slot resonance near emission source
Emission estimates	EE-001, EE-002	Board cavity resonance, switching harmonic envelope

Advisory outputs (not findings):

Pre-compliance test plan — frequency band prioritization, interface risk ranking, near-field probe points
Regulatory coverage — market-to-standards mapping, coverage matrix (what the tool checks vs what requires lab testing)

涵盖18个类别的44个规则ID。每个规则都有特定阈值、原理和来源引用——详见

references/pcb-emc-rules.md

获取完整详情。

类别	规则	检测内容
接地平面	GP-001至GP-005	信号跨越空隙、区域碎片化、缺失接地平面、填充率低、多接地域
去耦	DC-001至DC-003	电容离IC过远、IC无去耦电容、电容离过孔过远
I/O滤波	IO-001、IO-002	连接器无滤波、接地引脚不足
开关EMC	SW-001至SW-003	谐波重叠、开关节点铜面积、输入电容环路面积
时钟布线	CK-001至CK-003	时钟位于外层、走线过长、时钟靠近连接器
过孔缝合	VS-001	接地过孔间距超过最高频率下的λ/20
叠层	SU-001至SU-003	相邻信号层、信号离参考平面过远、层间电容过薄
差分对	DP-001至DP-004	对内偏移超出协议限制、共模辐射、参考平面变更、外层布线
板边	BE-001至BE-003	信号靠近边缘、接地铺铜环不完整、连接器区域缝合
PDN阻抗	PD-001至PD-004	反谐振峰值、IC负载点的分布式电源轨阻抗、下游开关调节器的跨轨耦合
返回路径	RP-001	层转换过孔附近无接地缝合过孔
串扰	XT-001	3H间距违规、干扰源-受扰对
EMI滤波器	EF-001、EF-002	滤波器截止频率过于接近开关频率（分析或SPICE插入损耗）
ESD路径	ES-001、ES-002	TVS离连接器过远、TVS附近接地过孔不足
热-EMC	TH-001、TH-002	MLCC直流偏置降额（SRF偏移）、铁氧体靠近热源
屏蔽	SH-001	连接器孔径槽共振靠近发射源
发射估算	EE-001、EE-002	板腔共振、开关谐波包络

建议输出（非发现项）：

预合规测试计划 — 频段优先级、接口风险排名、近场探头点
法规覆盖 — 市场到标准的映射、覆盖矩阵（工具检查内容与需实验室测试内容对比）

Output Format

输出格式

json

{
  "summary": {
    "total_checks": 42,
    "critical": 2, "high": 5, "medium": 8, "low": 12, "info": 15,
    "emc_risk_score": 73
  },
  "target_standard": "fcc-class-b",
  "findings": [
    {
      "category": "ground_plane",
      "severity": "CRITICAL",
      "rule_id": "GP-001",
      "title": "Signal crosses ground plane void",
      "description": "Net SPI_CLK crosses a 3.2mm gap in GND on In1.Cu",
      "components": ["U3", "U7"],
      "nets": ["SPI_CLK"],
      "recommendation": "Route around the gap, or fill the void"
    }
  ],
  "per_net_scores": [
    {"net": "SPI_CLK", "score": 67, "finding_count": 3, "rules": ["GP-001", "CK-001", "BE-001"]}
  ],
  "test_plan": {
    "frequency_bands": [{"band": "30-88 MHz", "risk_level": "high", "source_count": 12}],
    "interface_risks": [{"connector": "J1", "protocol": "USB", "risk_score": 8}],
    "probe_points": [{"ref": "L1", "x": 45.2, "y": 32.1, "reason": "switching inductor"}]
  },
  "regulatory_coverage": {
    "market": "us",
    "applicable_standards": ["FCC Part 15 Class B"],
    "coverage_matrix": [{"standard": "...", "coverage": "partial", "note": "..."}]
  }
}

json

{
  "summary": {
    "total_checks": 42,
    "critical": 2, "high": 5, "medium": 8, "low": 12, "info": 15,
    "emc_risk_score": 73
  },
  "target_standard": "fcc-class-b",
  "findings": [
    {
      "category": "ground_plane",
      "severity": "CRITICAL",
      "rule_id": "GP-001",
      "title": "Signal crosses ground plane void",
      "description": "Net SPI_CLK crosses a 3.2mm gap in GND on In1.Cu",
      "components": ["U3", "U7"],
      "nets": ["SPI_CLK"],
      "recommendation": "Route around the gap, or fill the void"
    }
  ],
  "per_net_scores": [
    {"net": "SPI_CLK", "score": 67, "finding_count": 3, "rules": ["GP-001", "CK-001", "BE-001"]}
  ],
  "test_plan": {
    "frequency_bands": [{"band": "30-88 MHz", "risk_level": "high", "source_count": 12}],
    "interface_risks": [{"connector": "J1", "protocol": "USB", "risk_score": 8}],
    "probe_points": [{"ref": "L1", "x": 45.2, "y": 32.1, "reason": "switching inductor"}]
  },
  "regulatory_coverage": {
    "market": "us",
    "applicable_standards": ["FCC Part 15 Class B"],
    "coverage_matrix": [{"standard": "...", "coverage": "partial", "note": "..."}]
  }
}

Severity Levels

严重程度等级

Severity	Meaning	Action
CRITICAL	Almost certain to cause EMC failure	Must fix before fabrication
HIGH	Very likely to cause issues	Strongly recommend fixing
MEDIUM	May cause issues depending on specifics	Review and assess
LOW	Minor risk, good practice	Fix if convenient
INFO	Informational — frequencies, estimates	Useful for lab prep

严重程度	含义	操作
CRITICAL（严重）	几乎肯定会导致EMC测试失败	制造前必须修复
HIGH（高）	极有可能引发问题	强烈建议修复
MEDIUM（中）	根据具体情况可能引发问题	评审并评估
LOW（低）	轻微风险，良好实践	方便时修复
INFO（信息）	信息性内容——频率、估算值	对实验室准备有用

Risk Score

风险评分

Each rule ID contributes at most 3 findings to the score (worst severity first). This prevents per-net rules like GP-001 from saturating the score on 2-layer boards. All findings are still reported — only the score is capped.

penalty = sum(worst 3 per rule × severity weight)

score = max(0, 100 - penalty)

. Scores below 50 indicate significant EMC risk.

每个规则ID最多贡献3个发现到评分中（取最严重的前3个）。这避免了像GP-001这样的单网络规则在双层板上使评分饱和。所有发现仍会被报告——仅评分会被限制。

惩罚值 = （每个规则最严重的3个发现 × 严重程度权重）之和

，

评分 = max(0, 100 - 惩罚值)

。评分低于50表示存在显著EMC风险。

Interpreting Results

解读结果

Ground plane findings — Any CRITICAL finding (signal crossing a void) is almost always a real problem. Fix unconditionally.

Decoupling findings — Distance-based findings have moderate false positive rates. A cap at 6mm may be fine for a low-speed IC but problematic for a 100MHz clock buffer. Use frequency context to prioritize.

I/O filtering — Highly relevant for cable-connected products. For board-to-board connections inside an enclosure, the risk is lower.

Diff pair findings — Protocol-specific skew limits are well-defined. USB HS (25ps), PCIe (5ps), Ethernet (50ps). Findings exceeding these limits are real issues.

PDN findings — Anti-resonance peaks are real and cause voltage droop. SPICE-verified findings are more accurate than analytical. If a peak is flagged, add a capacitor with SRF near the peak frequency.

Emission estimates — Order-of-magnitude estimates (±10-20 dB). Use them to prioritize frequency bands for pre-compliance testing, not to predict pass/fail.

接地平面发现 — 任何严重（CRITICAL）发现（信号跨越空隙）几乎都是实际问题。必须无条件修复。

去耦发现 — 基于距离的发现有中等误报率。对于低速IC，6mm的电容距离可能没问题，但对于100MHz时钟缓冲器则可能有问题。结合频率背景确定优先级。

I/O滤波 — 对带线缆连接的产品高度相关。对于外壳内的板对板连接，风险较低。

差分对发现 — 协议特定的偏移限制定义明确。USB HS（25ps）、PCIe（5ps）、以太网（50ps）。超出这些限制的发现是实际问题。

PDN发现 — 反谐振峰值是真实存在的，会导致电压下降。SPICE验证的发现比分析模型更准确。如果峰值被标记，添加一个SRF接近峰值频率的电容。

发射估算 — 数量级估算（±10-20 dB）。用于优先选择预合规测试的频段，而非预测合格/不合格。

EMC Standards

EMC标准

Standard	Flag	Use Case
FCC Part 15 Class B	`fcc-class-b`	US residential (default)
FCC Part 15 Class A	`fcc-class-a`	US commercial/industrial
CISPR 32 Class B	`cispr-class-b`	International (EU CE marking)
CISPR 32 Class A	`cispr-class-a`	International commercial
CISPR 25 Class 5	`cispr-25`	Automotive (strictest)
MIL-STD-461G RE102	`mil-std-461`	Military/defense

The

--market

flag maps markets to all applicable standards:

us

eu

automotive

medical

military

标准	标志	使用场景
FCC Part 15 Class B	`fcc-class-b`	美国住宅（默认）
FCC Part 15 Class A	`fcc-class-a`	美国商业/工业
CISPR 32 Class B	`cispr-class-b`	国际（欧盟CE标志）
CISPR 32 Class A	`cispr-class-a`	国际商业
CISPR 25 Class 5	`cispr-25`	汽车（最严格）
MIL-STD-461G RE102	`mil-std-461`	军事/国防

--market

标志将市场映射到所有适用标准：

us

、

eu

、

automotive

、

medical

、

military

。

Limitations

局限性

Cannot predict absolute emission levels better than ±10-20 dB
Cannot account for enclosure effects (shielding, apertures, seams)
Cannot predict cable radiation without knowing external cable routing
Cannot replace full-wave simulation for complex geometries
Cannot guarantee compliance — only accredited lab measurement can

无法预测绝对发射水平，误差优于±10-20 dB
无法考虑外壳效应（屏蔽、孔径、接缝）
不知道外部线缆布线时无法预测线缆辐射
无法替代复杂几何结构的全波仿真
无法保证合规性——只有经认可的实验室测量才能做到这一点

emc

Original

Translation

EMC Pre-Compliance Skill

EMC预合规分析工具

Related Skills

相关工具

Requirements

要求

Workflow

工作流程

Step 1: Run the analyzers

步骤1：运行分析器

Step 2: Run EMC analysis

步骤2：运行EMC分析

Recommended: auto-resolve inputs from the current run

推荐：自动解析当前运行的输入文件

Equivalent — explicit paths still accepted (and required if you want to

等效方式——仍接受显式路径（如果指向非当前运行或覆盖某个输入文件，则为必填）

point at a non-current run or override one input)

One-off JSON (bypasses the cache)

一次性JSON（绕过缓存）

SPICE-enhanced (improved PDN and filter accuracy)

SPICE增强版（提升PDN和滤波精度）

Select target standard

选择目标标准

Select target market (sets all applicable standards)

选择目标市场（设置所有适用标准）

Filter by severity

按严重程度过滤

Human-readable text output

人类可读文本输出

Step 3: Interpret results

步骤3：解读结果

What Gets Checked

检查内容

Output Format

输出格式

Severity Levels

严重程度等级

Risk Score

风险评分

Interpreting Results

解读结果

EMC Standards

EMC标准

Limitations

局限性