spice-sim

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🇺🇸

Original

English

🇨🇳

Translation

Chinese

Spice Simulation

Spice 仿真

Add a small ngspice-backed testbench to a

.zen

design.

为

.zen

设计添加一个基于ngspice的小型测试台。

Workflow

工作流

Confirm the target is simulation-capable by runnnig a dummy sim.
```
pcb sim <path/to/file.zen> --setup "* empty setup check"
```
If the SPICE model is missing, add it. Find a vendor model, download it, or create a simple behavioral model if needed. Wire it through the leaf component with
```
spice_model=SpiceModel(...)
```
before writing the testbench.
Create a focused testbench file. Use a generic package-local path such as
```
<package>/testbench/test_<scenario>.zen
```
.
Keep the structure simple:

top docstring
imports
nets/interfaces
module-under-test instantiation
minimal external load or pull-ups
one
```
Simulation(...)
```
block

Put sources and analysis inside
```
Simulation.setup
```
. Use raw ngspice for:

```
DC
```
```
PULSE(...)
```
```
PWL(...)
```
```
.control
```
```
tran
```
```
hardcopy
```

Write the plot to
```
testbench/output/<scenario>.svg
```
.

通过运行空仿真确认目标支持仿真：

pcb sim <path/to/file.zen> --setup "* empty setup check"

如果缺少SPICE模型，请添加。查找供应商模型并下载，必要时也可以创建简单的行为模型。编写测试台之前，通过
```
spice_model=SpiceModel(...)
```
将其绑定到叶子组件。
创建专用的测试台文件。使用通用的包本地路径，例如
```
<package>/testbench/test_<scenario>.zen
```
。
保持结构简洁：

顶部文档字符串
导入声明
网络/接口
待测模块实例化
最少的外部负载或上拉电阻
一个
```
Simulation(...)
```
块

将源和分析指令放在
```
Simulation.setup
```
中。直接使用ngspice语法编写以下内容：

```
DC
```
```
PULSE(...)
```
```
PWL(...)
```
```
.control
```
```
tran
```
```
hardcopy
```

将绘制的图表输出到
```
testbench/output/<scenario>.svg
```
。

Simulation In Zener

Zener中的仿真

Simulation

is a Zener property loaded from

@stdlib/properties.zen

and attached as a normal top-level object:

python

load("@stdlib/properties.zen", "Simulation")

Simulation(
    name="SIM",
    setup="""
* raw ngspice goes here
.control
  tran 10u 10m
.endc
""",
)

The

setup

string is passed through as ngspice input. Put voltage sources, waveform definitions, analysis commands, and plot/export commands there.

Simulation

是从

@stdlib/properties.zen

加载的Zener属性，可作为普通顶层对象挂载：

python

load("@stdlib/properties.zen", "Simulation")

Simulation(
    name="SIM",
    setup="""
* raw ngspice goes here
.control
  tran 10u 10m
.endc
""",
)

setup

字符串会直接作为ngspice输入传递。你可以在其中放置电压源、波形定义、分析命令以及绘图/导出命令。

Pattern

示例模式

python

"""<Part> <scenario> simulation test."""

load("@stdlib/interfaces.zen", "Ground", "Power")
load("@stdlib/units.zen", "Voltage")
load("@stdlib/properties.zen", "Simulation")

Target = Module("../Target.zen")
Resistor = Module("@stdlib/generics/Resistor.zen")

VIN = Power("VIN", voltage=Voltage("12V"))
VOUT = Power("VOUT")
GND = Ground("GND")

Target(
    name="UUT",
    VIN=VIN,
    VOUT=VOUT,
    GND=GND,
)

Resistor(
    name="R_LOAD",
    value="10ohm",
    package="0603",
    P1=VOUT,
    P2=GND,
)

Simulation(
    name="SIM",
    setup="""
* <Part> <scenario>

V_IN VIN GND DC 12

.control
  tran 10u 10m

  set hcopydevtype = svg
  hardcopy output/<scenario>.svg v(VIN) v(VOUT) title "<Part> <scenario>" xlabel "Time" ylabel "Voltage"
.endc

""",
)

python

"""<Part> <scenario> simulation test."""

load("@stdlib/interfaces.zen", "Ground", "Power")
load("@stdlib/units.zen", "Voltage")
load("@stdlib/properties.zen", "Simulation")

Target = Module("../Target.zen")
Resistor = Module("@stdlib/generics/Resistor.zen")

VIN = Power("VIN", voltage=Voltage("12V"))
VOUT = Power("VOUT")
GND = Ground("GND")

Target(
    name="UUT",
    VIN=VIN,
    VOUT=VOUT,
    GND=GND,
)

Resistor(
    name="R_LOAD",
    value="10ohm",
    package="0603",
    P1=VOUT,
    P2=GND,
)

Simulation(
    name="SIM",
    setup="""
* <Part> <scenario>

V_IN VIN GND DC 12

.control
  tran 10u 10m

  set hcopydevtype = svg
  hardcopy output/<scenario>.svg v(VIN) v(VOUT) title "<Part> <scenario>" xlabel "Time" ylabel "Voltage"
.endc

""",
)

Component Pattern

组件模式

If the leaf component does not already expose a SPICE model, add one like this:

python

VIN = io("VIN", Net)
VOUT = io("VOUT", Net)
GND = io("GND", Net)

Component(
    name="MyPart",
    symbol=Symbol(library="MyPart.kicad_sym"),
    pins={"VIN": VIN, "VOUT": VOUT, "GND": GND},
    spice_model=SpiceModel(
        "MyPart.lib",
        "MyPart_SUBCKT",
        nets=[VIN, VOUT, GND],
        args={},
    ),
)

如果叶子组件尚未提供SPICE模型，可以按如下方式添加：

python

VIN = io("VIN", Net)
VOUT = io("VOUT", Net)
GND = io("GND", Net)

Component(
    name="MyPart",
    symbol=Symbol(library="MyPart.kicad_sym"),
    pins={"VIN": VIN, "VOUT": VOUT, "GND": GND},
    spice_model=SpiceModel(
        "MyPart.lib",
        "MyPart_SUBCKT",
        nets=[VIN, VOUT, GND],
        args={},
    ),
)

Example Shapes

示例波形

Load switch enable test:

spice

V_IN VIN GND DC 5.3
V_ON ON GND PULSE(0 0.9V 1ms 10us 10us 3ms 5ms)

Protection threshold sweep:

spice

V_IN VIN GND PWL(0 12 5m 12 5.1m 22 10m 22 10.1m 12 15m 12 15.1m 2 20m 2)

负载开关启用测试：

spice

V_IN VIN GND DC 5.3
V_ON ON GND PULSE(0 0.9V 1ms 10us 10us 3ms 5ms)

保护阈值扫描：

spice

V_IN VIN GND PWL(0 12 5m 12 5.1m 22 10m 22 10.1m 12 15m 12 15.1m 2 20m 2)

Notes

注意事项

Prefer one behavior per file: startup, enable/disable, OVLO/UVLO, current limit.
Keep passives in Zener and keep sources in
```
setup
```
.
Plot only the signals that prove the behavior.
If a SPICE model is missing, obtain or create it first, then add the testbench.

每个文件尽量只测试一种行为：启动、启用/禁用、过压保护/欠压保护、电流限制。
将无源元件保留在Zener中，将源放在
```
setup
```
中。
仅绘制可验证行为的信号。
如果缺少SPICE模型，请先获取或创建模型，再添加测试台。