eda-pcb

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Original

English

🇨🇳

Translation

Chinese

EDA PCB Skill

EDA PCB 技能

PCB layout, component placement, and routing.

PCB布局、元件放置与布线。

Auto-Activation Triggers

自动触发条件

This skill activates when:

User asks to "layout PCB", "place components", "route traces"
User is working with
```
.kicad_pcb
```
files
User asks about placement, routing, copper pours, vias
Project has schematic but no PCB layout
User mentions DFM, trace width, or clearance

满足以下条件时，该技能将激活：

用户提出“进行PCB布局”、“放置元件”、“走线布线”等需求
用户正在处理
```
.kicad_pcb
```
文件
用户咨询放置、布线、覆铜、过孔相关问题
项目已有原理图但未进行PCB布局
用户提及DFM、走线宽度或间距要求

Context Requirements

上下文要求

Requires:

```
hardware/*.kicad_sch
```
- Completed schematic with netlist
```
docs/component-selections.md
```
- Component details
```
docs/design-constraints.json
```
- Board size, layer count, etc.
```
datasheets/
```
- For placement/routing recommendations

Produces:

```
hardware/*.kicad_pcb
```
- KiCad PCB file
```
docs/pcb-status.md
```
- Layout progress tracking

所需文件/信息：

```
hardware/*.kicad_sch
```
- 已完成且带有网表的原理图
```
docs/component-selections.md
```
- 元件详细信息
```
docs/design-constraints.json
```
- 板卡尺寸、层数等设计约束
```
datasheets/
```
- 用于参考元件放置/布线建议

生成文件：

```
hardware/*.kicad_pcb
```
- KiCad格式的PCB文件
```
docs/pcb-status.md
```
- 布局进度跟踪文档

Workflow

工作流

1. Load Context

1. 加载上下文信息

@docs/design-constraints.json
@docs/component-selections.md
@docs/schematic-status.md
@datasheets/ (for placement guidance)

@docs/design-constraints.json
@docs/component-selections.md
@docs/schematic-status.md
@datasheets/ (for placement guidance)

1.5 Pre-Layout Validation

1.5 布局前验证

Before starting layout, verify:

Check	Source	Action if Missing
Schematic ERC clean	schematic-status.md	Complete schematic first
Layer count decided	design-constraints.json	See `LAYER-COUNT-DECISION.md`
Stackup selected	design-constraints.json	See `STACKUP-DECISION.md`
Board dimensions	design-constraints.json	Define constraints
Critical interfaces	design-constraints.json	USB, SPI speeds, etc.
Thermal budget	design-constraints.json	Power dissipation known

Extract key constraints:

json

{
  "board": {
    "layers": 4,
    "thickness": 1.6,
    "dimensions": {"width": 50, "height": 40}
  },
  "dfmTargets": {
    "manufacturer": "JLCPCB",
    "minTraceWidth": 0.15,
    "minClearance": 0.15,
    "impedanceControl": true
  },
  "interfaces": {
    "usb": true,
    "highSpeedSpi": false
  },
  "thermal": {
    "maxPowerDissipation": 2.5
  }
}

Architecture Validation Warnings:

Condition	Warning
USB + 2-layer board	Cannot achieve 90Ω impedance
Buck converter + no ground plane	EMI issues likely
WiFi/BLE + 2-layer	Antenna performance degraded
High-speed SPI (>20MHz) + long traces	Signal integrity risk
No thermal plan + >1W dissipation	Thermal issues likely

开始布局前，请验证以下内容：

检查项	来源	缺失时的操作
原理图ERC检查无错误	schematic-status.md	先完成原理图设计
已确定层数	design-constraints.json	参考 `LAYER-COUNT-DECISION.md`
已选择层叠结构	design-constraints.json	参考 `STACKUP-DECISION.md`
已定义板卡尺寸	design-constraints.json	明确设计约束
已确定关键接口	design-constraints.json	USB、SPI速率等
已确定热预算	design-constraints.json	明确功耗限制

提取关键约束：

json

{
  "board": {
    "layers": 4,
    "thickness": 1.6,
    "dimensions": {"width": 50, "height": 40}
  },
  "dfmTargets": {
    "manufacturer": "JLCPCB",
    "minTraceWidth": 0.15,
    "minClearance": 0.15,
    "impedanceControl": true
  },
  "interfaces": {
    "usb": true,
    "highSpeedSpi": false
  },
  "thermal": {
    "maxPowerDissipation": 2.5
  }
}

架构验证警告：

情况	警告内容
USB接口+双层板	无法实现90Ω阻抗匹配
降压转换器+无地平面	可能存在EMI问题
WiFi/BLE+双层板	天线性能会下降
高速SPI(>20MHz)+长走线	存在信号完整性风险
无热设计方案+功耗>1W	可能存在热问题

2. Initialize PCB

2. 初始化PCB

Create PCB file or open existing
Import netlist from schematic
Set board outline per constraints
Configure layer stackup
Set design rules

创建新的PCB文件或打开已有文件
从原理图导入网表
根据设计约束设置板卡外形
配置层叠结构
设置设计规则

3. Configure Design Rules

3. 配置设计规则

Set rules appropriate for manufacturer:

JLCPCB standard:
- Min trace width: 0.127mm (5mil)
- Min clearance: 0.127mm (5mil)
- Min via drill: 0.3mm
- Min via annular ring: 0.13mm

根据制造商要求设置规则：

JLCPCB standard:
- Min trace width: 0.127mm (5mil)
- Min clearance: 0.127mm (5mil)
- Min via drill: 0.3mm
- Min via annular ring: 0.13mm

4. Place Components

4. 放置元件

Priority order:

Fixed position items - Connectors (edge), mounting holes
MCU/Main IC - Central location
Crystal/oscillator - Within 5mm of MCU
Power components - Near input, thermal considerations
Decoupling capacitors - Adjacent to IC power pins
Sensitive analog - Away from noisy digital
Remaining components - Grouped by function

See

reference/PLACEMENT-STRATEGY.md

for detailed guidelines.

优先级顺序：

固定位置元件 - 边缘连接器、安装孔
MCU/主芯片 - 放置在中心位置
晶振/振荡器 - 放置在MCU 5mm范围内
电源元件 - 靠近输入接口，考虑热设计
去耦电容 - 紧邻IC电源引脚
敏感模拟元件 - 远离数字电路
其余元件 - 按功能分组放置

详细指导请参考

reference/PLACEMENT-STRATEGY.md

。

5. Route Critical Signals First

5. 优先布线关键信号

Priority:

Power delivery (wide traces, pours)
Crystal/oscillator (short, guarded)
USB differential pairs (90Ω impedance)
High-speed signals (length matching)
Sensitive analog (away from digital)
General signals

See

reference/ROUTING-RULES.md

for trace width and clearance guidelines.

优先级：

电源通路（宽走线、覆铜）
晶振/振荡器（短走线、屏蔽）
USB差分对（90Ω阻抗）
高速信号（等长走线）
敏感模拟信号（远离数字电路）
普通信号

走线宽度与间距指导请参考

reference/ROUTING-RULES.md

。

6. Create Copper Pours

6. 创建覆铜

GND pour on bottom layer (2-layer)
Or GND on layer 2, power on layer 3 (4-layer)
Thermal relief on pads
Stitch vias for plane continuity

双层板：底层覆GND
四层板：第二层覆GND，第三层覆电源
焊盘采用热焊盘连接
使用缝合过孔保证平面连通性

7. Route Remaining Signals

7. 布线剩余信号

Follow schematic groupings
Minimize vias
Avoid acute angles (use 45°)
Keep trace lengths reasonable

按照原理图的功能分组布线
尽量减少过孔使用
避免锐角走线（采用45°角）
控制走线长度在合理范围

8. DRC Check

8. DRC检查

Run design rule check
Fix violations
Document intentional exceptions

运行设计规则检查
修复违规项
记录有意保留的例外情况

9. Visual Review

9. 视觉检查

Generate board images
Check silkscreen readability
Verify component orientation marks
Review for manufacturing issues

生成板卡图像
检查丝印可读性
验证元件方向标识
检查是否存在可制造性问题

10. Pre-Manufacturing Review

10. 制造前审核

Validation checklist before ordering:

Category	Check	Reference
DRC	0 errors, 0 warnings	`DRC-VIOLATIONS-GUIDE.md`
Clearances	Meet manufacturer minimums	`DFM-RULES.md`
Via sizes	Drill ≥ 0.3mm (JLCPCB std)	`DFM-RULES.md`
Annular rings	≥ 0.13mm (1oz copper)	`DFM-RULES.md`
Trace widths	Power traces sized for current	`ROUTING-RULES.md`
USB traces	90Ω impedance, length matched	`HIGH-SPEED-ROUTING.md`
Silkscreen	Not on pads, readable	Visual check
Board outline	Closed shape, proper clearance	`DFM-RULES.md`

Thermal verification:

Power components have thermal relief
Thermal vias under QFN/thermal pads
Heat sink areas connected to copper pour
No thermal bottlenecks (narrow traces for high current)

Signal integrity verification:

High-speed signals over solid ground
Return paths not broken by splits
Crystal area guarded, no traces crossing
Antenna keep-out respected (if applicable)

下单前验证清单：

类别	检查项	参考文档
DRC检查	0错误、0警告	`DRC-VIOLATIONS-GUIDE.md`
间距	满足制造商最小值	`DFM-RULES.md`
过孔尺寸	钻孔≥0.3mm（JLCPCB标准）	`DFM-RULES.md`
过孔环宽	≥0.13mm（1盎司铜）	`DFM-RULES.md`
走线宽度	电源走线满足载流要求	`ROUTING-RULES.md`
USB走线	90Ω阻抗、等长走线	`HIGH-SPEED-ROUTING.md`
丝印	未覆盖焊盘、可读性良好	视觉检查
板卡外形	闭合形状、间距合理	`DFM-RULES.md`

热设计验证：

电源元件采用热焊盘连接
QFN/热焊盘下方有散热过孔
散热区域与覆铜连接
大电流走线无瓶颈（窄走线）

信号完整性验证：

高速信号走在完整地平面上
回流路径未被分割打断
晶振区域已屏蔽，无走线穿过
遵守天线禁布区要求（如有）

Output Format

输出格式

pcb-status.md

markdown

undefined

markdown

undefined

PCB Layout Status

PCB布局状态

Project: [name] Updated: [date]

项目：[名称] 更新时间：[日期]

Board Specifications

板卡规格

Size: X × Y mm
Layers: N
Thickness: 1.6mm

尺寸：X × Y 毫米
层数：N
厚度：1.6毫米

Progress

进度

Layer Usage

层使用情况

Layer	Usage
F.Cu	Signals, components
B.Cu	GND pour, some signals

层	用途
F.Cu	信号、元件
B.Cu	GND覆铜、部分信号

DRC Status

DRC状态

Errors: X
Warnings: Y
Unrouted nets: Z

错误数：X
警告数：Y
未布线网络数：Z

Design Rules

设计规则

Trace width: 0.2mm (signals), 0.5mm (power)
Clearance: 0.2mm
Via: 0.3mm drill, 0.6mm pad

走线宽度：0.2毫米（信号）、0.5毫米（电源）
间距：0.2毫米
过孔：钻孔0.3毫米，焊盘0.6毫米

Notes

备注

[Any special considerations]

[特殊注意事项]

Next Steps

下一步计划

[What remains to be done]

undefined

[待完成事项]

undefined

Guidelines

指导原则

Always check datasheets for recommended layouts
Keep high-current paths short and wide
Maintain ground plane integrity under sensitive signals
Consider thermal management early
Use the DRC frequently during layout

始终参考数据手册中的推荐布局
大电流通路应短而宽
敏感信号下方的地平面需保持完整
尽早考虑热管理设计
布局过程中频繁使用DRC检查

Reference Documents

参考文档

Document	Purpose
`reference/PLACEMENT-STRATEGY.md`	Component placement guidelines
`reference/ROUTING-RULES.md`	Trace width and routing rules
`reference/EMI-CONSIDERATIONS.md`	EMI/EMC best practices
`reference/DFM-RULES.md`	Design for manufacturing rules
`reference/DRC-VIOLATIONS-GUIDE.md`	Common DRC errors and fixes
`reference/STACKUP-DECISION.md`	Layer stackup selection
`reference/HIGH-SPEED-ROUTING.md`	USB, SPI, I2C, antenna routing

Upstream documents:

Document	What to Extract
`LAYER-COUNT-DECISION.md` (eda-architect)	Layer count rationale
`THERMAL-BUDGET.md` (eda-architect)	Power dissipation limits
`DECOUPLING-STRATEGY.md` (eda-research)	Cap values and placement
`SCHEMATIC-REVIEW-CHECKLIST.md` (eda-schematics)	Pre-layout verification

文档	用途
`reference/PLACEMENT-STRATEGY.md`	元件放置指导
`reference/ROUTING-RULES.md`	走线宽度与布线规则
`reference/EMI-CONSIDERATIONS.md`	EMI/EMC最佳实践
`reference/DFM-RULES.md`	可制造性设计规则
`reference/DRC-VIOLATIONS-GUIDE.md`	常见DRC错误及修复方法
`reference/STACKUP-DECISION.md`	层叠结构选择
`reference/HIGH-SPEED-ROUTING.md`	USB、SPI、I2C、天线布线

上游文档：

文档	提取内容
`LAYER-COUNT-DECISION.md` (eda-architect)	层数选择依据
`THERMAL-BUDGET.md` (eda-architect)	功耗限制
`DECOUPLING-STRATEGY.md` (eda-research)	电容值与放置方式
`SCHEMATIC-REVIEW-CHECKLIST.md` (eda-schematics)	布局前验证项

Next Steps

后续步骤

After PCB layout is complete:

Run
```
/eda-check
```
for comprehensive validation
Update
```
design-constraints.json
```
stage to "validation"

PCB布局完成后：

运行
```
/eda-check
```
进行全面验证
将
```
design-constraints.json
```
中的阶段更新为"validation"