dma-baremetal

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Original

English

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Translation

Chinese

DMA (Bare-Metal)

DMA（裸机）

Purpose

用途

Configure DMA controllers for memory-to-peripheral and peripheral-to-memory transfers: channel/stream setup, burst sizes, circular mode, half-transfer interrupts, and cache coherency on Cortex-M7.

配置DMA控制器以实现内存到外设及外设到内存的传输：通道/流设置、突发大小、循环模式、半传输中断，以及Cortex-M7上的缓存一致性。

When to Use

适用场景

Offloading UART/SPI/ADC bulk transfers from CPU
Audio/streaming double buffers
Debugging DMA not triggering or corrupt data

将UART/SPI/ADC批量传输任务从CPU卸载
音频/流处理双缓冲
调试DMA未触发或数据损坏问题

Workflow

工作流程

1. STM32 DMA2 stream (periph→mem)

1. STM32 DMA2流（外设→内存）

/* UART2 RX DMA — Stream5, Channel 4 (verify RM matrix) */
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;

DMA1_Stream5->PAR  = (uint32_t)&USART2->DR;
DMA1_Stream5->M0AR = (uint32_t)rx_buf;
DMA1_Stream5->NDTR = sizeof(rx_buf);
DMA1_Stream5->CR   = DMA_SxCR_MINC     /* mem increment */
                   | DMA_SxCR_TCIE    /* transfer complete IRQ */
                   | DMA_SxCR_CHSEL_2 /* channel 4 */
                   | DMA_SxCR_EN;

USART2->CR3 |= USART_CR3_DMAR;

/* UART2 RX DMA — Stream5, Channel 4 (verify RM matrix) */
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;

DMA1_Stream5->PAR  = (uint32_t)&USART2->DR;
DMA1_Stream5->M0AR = (uint32_t)rx_buf;
DMA1_Stream5->NDTR = sizeof(rx_buf);
DMA1_Stream5->CR   = DMA_SxCR_MINC     /* mem increment */
                   | DMA_SxCR_TCIE    /* transfer complete IRQ */
                   | DMA_SxCR_CHSEL_2 /* channel 4 */
                   | DMA_SxCR_EN;

USART2->CR3 |= USART_CR3_DMAR;

2. Circular / double buffer

2. 循环/双缓冲

DMA1_Stream5->CR |= DMA_SxCR_CIRC;  /* auto-reload NDTR */
/* HTIF = first half, TCIF = second half — process in IRQ */

DMA1_Stream5->CR |= DMA_SxCR_CIRC;  /* auto-reload NDTR */
/* HTIF = first half, TCIF = second half — process in IRQ */

3. Cortex-M7 cache (H7)

3. Cortex-M7缓存（H7系列）

DMA buffer in non-cacheable region or clean/invalidate D-Cache:

SCB_CleanDCache_by_Addr((void*)tx_buf, len);
/* after DMA TX */
SCB_InvalidateDCache_by_Addr((void*)rx_buf, len);

DMA缓冲区需置于非缓存区域，或清理/无效化数据缓存：

SCB_CleanDCache_by_Addr((void*)tx_buf, len);
/* after DMA TX */
SCB_InvalidateDCache_by_Addr((void*)rx_buf, len);

4. Agent usage

4. Agent使用方式

/dma-baremetal Configure UART RX DMA circular buffer on STM32F4

/dma-baremetal Configure UART RX DMA circular buffer on STM32F4

Common Problems

常见问题

Symptom	Cause	Fix
DMA no start	Stream/channel mismatch	RM DMA request mapping table
Corrupt RX	Cache coherency (M7)	Invalidate after RX complete
NDTR stuck	Peripheral DMA enable missing	USART_CR3 DMAR/DMAT
IRQ flood	Clear flags in ISR	`DMA_LISR` / `HIFCR`

症状	原因	解决方法
DMA无法启动	流/通道不匹配	参考参考手册（RM）的DMA请求映射表
接收数据损坏	缓存一致性问题（M7系列）	接收完成后执行无效化操作
NDTR值卡住	未启用外设DMA	设置USART_CR3的DMAR/DMAT位
中断泛滥	未在中断服务程序（ISR）中清除标志位	使用 `DMA_LISR` / `HIFCR` 清除标志